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Description: FPGA底层的USB接口芯片的驱动，用于向上位机传送数据。-Driving USB interface chip FPGA bottom, used to transmit data to the host computer.
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Size: 2196480 |
Author: 张仰望 |
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Description: 基于FPGA的对Cyprerss公司的USB芯片的驱动，velilog代码-FPGA driver for Cyprerss company based on USB chip, velilog code
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Size: 206848 |
Author: 王洛 |
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Description: usb回环程序，数据通过usb传到fpga再把数据传回usb-Usb loopback program, data via usb to fpga and the data back to the usb
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Size: 480256 |
Author: wangcheng |
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Description: 本代码为DE2开发板例程源码（EP2C35F672C6），项目基于quartus II 9.0（随板光盘为7.2版本以下，在9.0版以上编译会报错）。本项目实现一个USB画笔功能，通过FPGA控制USB口，USB口接上鼠标，通过XGA口外界显示设备，实现显示设备对鼠标移动轨迹的显示。-In this demonstration, we implement a Paintbrush application by using a USB mouse as the input device.This demonstration uses the device port of the Philips ISP1362 chip and the Nios II processor to implement a USB mouse movement detector. We also implemented a video frame buffer with a VGA controller to perform the real-time image storage and display.
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Size: 2547712 |
Author: chenxin |
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Description: EZ-USB FX3 与FPGA通讯官方例程，包括了短包发送，ZLP发送，LoopBack例程，包括完整的GPIF设计，代码和开发文档-EZ-USB FX3 and FPGA communications official routines, including a short packet is sent, ZLP send, LoopBack routines, including complete GPIF design, code and development documentation
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Size: 6426624 |
Author: zhoujun |
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Description: usb控制器，采用FPGA实现，完整项目包-USB controler
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Size: 3840000 |
Author: 于斌 |
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Description: 该代码实现了FPGA对USB芯片68013的读写，语言是VERLOD，试验通过。-The code to achieve the FPGA read and write 68013 on the USB chip, the language is VERLOD, through the test.
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Size: 4414464 |
Author: MR.JHY |
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Description: 通过FPGA控制USB实现Slave FIFO模式下的数据传输-achieve the data sending and recieving throgh FPGA by controling the USB working in the Slave FIFO mode
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Size: 1024 |
Author: Nianhai Zhang |
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Description: 用VERILOG HDL语言写的usb程序。FPGA芯片用的是ALTERA公司的，编程所用的软件为quartus和nios，USB芯片为CH376.-VERILOG HDL language written with usb program. ALTERA FPGA chip using the company s software program used quartus and nios, USB chip CH376.
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Size: 6358016 |
Author: 周燕 |
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Description: 这是基于FPGA的USB通讯程序。通过在quartus中建立SOPC，建立PIO口，并在NIOS中写驱动和寄存器等，实现USB通信。经检验，该程序通信正常。-This is FPGA-based USB communication program. By establishing the quartus in SOPC, establish PIO mouth and NIOS to write drivers and registers, realize USB communications. Upon examination, the program can communicate.
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Size: 18978816 |
Author: 周燕 |
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Description: Zynq Mini-ITX 单芯片可编程SOC(ARM+FPGA)开发板电路原理图 -Zynq Mini-ITX Development Board Schematics
the Zynq Mini-ITX development board features 2 GB DDR3 SDRAM, PCIe Gen2 x16 Root
Complex slot (x4 electrical), SATA-III interface, SFP interface, QSPI Flash memory,
HDMI interface, LVDS touch panel interface, Audio Codec, a 10/100/1000 Ethernet
PHY, a USB 2.0 4-port hub, a microSD card interface, and a USB-UART port.
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Size: 2623488 |
Author: 王广龙 |
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Description: EasyGX Cyclone® IV GX电路原理图，包括基于FPGA的PCI Express和10/100/1000M以太网接口相关电路。-The EasyGX Cyclone® IV GX development kit is especially suitable for develop and test PCI Express and 10/100/1000M Ethernet interface, including NIOS II embedded CPU and USB-Blaster function, which provided rich external memory for rapid prototype environment.
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Size: 220160 |
Author: 王广龙 |
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Description: 文章推荐： 采用CMOS探测器，低功耗FPGA、FX2-USB、无线电数据传输等技术，胶囊相机的演示板，非常值得推荐
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Size: 668672 |
Author: Peter |
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Description: 单片机开发源码，用于实现FPGA数据向单片机发送数据，转换成USB协议后传输到电脑上-MCU development source for implementing FPGA data to the microcontroller to send data, convert the USB protocol transmitted to the computer
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Size: 139264 |
Author: 刘万利 |
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Description: 基于xilinx FPGA 的USB开发，实测好用-xilinx USB development, available
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Size: 544768 |
Author: peisongwei |
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Description: 基于altera公司MAX10型FPGA的usb至sdhc通信的调试程序-Altera company based debugger MAX 10 type of FPGA to sdhc usb communication
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Size: 2832384 |
Author: qiqi |
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Description: 完全用verliog写的FPGA和CH372与电脑USB设备通信。可以和电脑收发数据，已经测试成功，如有疑问留言，程序可能有点乱，-Written entirely in verilog FPGA and CH372 USB devices to communicate with the computer. And computers can send and receive data, it has been tested successfully, if in doubt leave a message, the program may be a bit messy,
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Size: 5426176 |
Author: 高政 |
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Description: The Butterfly Light is an open source, modular FPGA development board. It is comprised of the USB Cocoon and the Spartan 3E Cocoon which paired together create the Butterfly Light FPGA development board. The Butterfly Light is best suited for developers who prefer to create their own daughterboards instead of utilizing the Wing peripheral system. The Butterfly Light exposes the maximum amount of I/O of all available Butterflies. It is also well suited for use with the Logic Analyzer software which implements a 100Mhz, 32 channel Logic Analyzer.-The Butterfly Light is an open source, modular FPGA development board. It is comprised of the USB Cocoon and the Spartan 3E Cocoon which paired together create the Butterfly Light FPGA development board. The Butterfly Light is best suited for developers who prefer to create their own daughterboards instead of utilizing the Wing peripheral system. The Butterfly Light exposes the maximum amount of I/O of all available Butterflies. It is also well suited for use with the Logic Analyzer software which implements a 100Mhz, 32 channel Logic Analyzer.
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Size: 198656 |
Author: Joe |
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Description: The uTosNet framework aims at providing a very fast method for interfacing physical components, such as motor drivers, ADCs, encoders, and similar, to applications on a PC.
The framework is based on the Node-on-Chip architecture (link to paper coming).
It works by utilizing a dual-port BlockRam in the FPGA, with one port exposed to access the PC (through uTosNet) and the other port exposed to access user-defined modules. This allows easy and generic storage of process variables.
Currently two versions of uTosNet are supported:
PC side USB converter chip UART FPGA
PC side Ethernet Digi Connect ME 9210 microcontroller module SPI FPGA-The uTosNet framework aims at providing a very fast method for interfacing physical components, such as motor drivers, ADCs, encoders, and similar, to applications on a PC.
The framework is based on the Node-on-Chip architecture (link to paper coming).
It works by utilizing a dual-port BlockRam in the FPGA, with one port exposed to access the PC (through uTosNet) and the other port exposed to access user-defined modules. This allows easy and generic storage of process variables.
Currently two versions of uTosNet are supported:
PC side USB converter chip UART FPGA
PC side Ethernet Digi Connect ME 9210 microcontroller module SPI FPGA
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Size: 7190528 |
Author: Joe |
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Description: cypress官方提供的几篇应用笔记，包括EZ-USB入门及EZ-USB与在FPGA上的应用及固件开发等。-Cypress official offers several application notes, including the introduction of EZ-USB and EZ-USB and the application of FPGA and firmware development, etc..
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Size: 7753728 |
Author: PrudentMe |
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